In recent years, there has been proposed a technique of using a double-gate Fin-MOSFET (hereinafter, also “FinFET”) as a fully-depleted channel MOSFET (hereinafter, also “FD transistor”). The FinFET serving as an FD transistor is advantageous over an FD planar transistor in suppression of a short channel effect and therefore it is suited for device downscaling.
Meanwhile, there has been proposed a technique for dynamically controlling a threshold voltage of a semiconductor device typified by a MOSFET by applying a temporally changing substrate voltage to a partial well of the MOSFET or a technique (power gating) for controlling a threshold voltage of a switching transistor by applying a substrate voltage to a well and cutting off a power supply line itself. In an examples of the latter technique (power gating), the substrate voltage allows easily to turn off a power switching transistor for low power consumption when the MOSFET is on a standby state.
However, it is difficult to control the threshold voltage of an FD transistor by a substrate voltage for the following reason. In case of an FD planar MOSFET (R. Tsuchiya et al, “Controllable Inverter Delay and Suppressing Vth Fluctuation Technology in Silicon on Thin BOX Featuring Dual Back-Gate Bias Architecture”, International Electron Devices Meeting (IEDM) 2007, 475-478) or FD FinFET formed on an SOI (Silicon On Insulator) substrate, a substrate bias cannot be applied to a channel part due to its structure. Further, when the substrate voltage is applied via the well region, it is also difficult to control threshold voltage only for the power switching transistor without influencing the other transistors in a logic circuit.
In case of an FD MOSFET formed on a thin film SOI substrate, it is necessary to provide a thin film BOX (Buried Oxide) layer right under the channel part so as to control the threshold voltage or the like using the substrate voltage. However, the SOI substrate having a thin film BOX layer formed thereon is generally expensive, considering the total manufacturing cost.
Accordingly, it is disadvantageously difficult to selectively control the threshold voltage of the power switching transistor in the logic circuit constituted by FD transistors or costs increase disadvantageously. That is, it has been difficult to apply the power gating technique to a logic circuit constituted by FD transistors.